Commit a03cd57a authored by Bc. Petr Elexa's avatar Bc. Petr Elexa

panel: Add headers for lpc chip lib

parent 561af22d
This diff is collapsed.
/*
* @brief LPC11xx CCAN ROM API declarations and functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CCAND_11XX_H_
#define __CCAND_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CCANROM_11XX CHIP: LPC11xx CCAN ROM Driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* CCAN ROM error status bits
*/
#define CAN_ERROR_NONE 0x00000000UL
#define CAN_ERROR_PASS 0x00000001UL
#define CAN_ERROR_WARN 0x00000002UL
#define CAN_ERROR_BOFF 0x00000004UL
#define CAN_ERROR_STUF 0x00000008UL
#define CAN_ERROR_FORM 0x00000010UL
#define CAN_ERROR_ACK 0x00000020UL
#define CAN_ERROR_BIT1 0x00000040UL
#define CAN_ERROR_BIT0 0x00000080UL
#define CAN_ERROR_CRC 0x00000100UL
/**
* CCAN ROM control bits for CAN_MSG_OBJ.mode_id
*/
#define CAN_MSGOBJ_STD 0x00000000UL /* CAN 2.0a 11-bit ID */
#define CAN_MSGOBJ_EXT 0x20000000UL /* CAN 2.0b 29-bit ID */
#define CAN_MSGOBJ_DAT 0x00000000UL /* data frame */
#define CAN_MSGOBJ_RTR 0x40000000UL /* rtr frame */
typedef struct CCAN_MSG_OBJ {
uint32_t mode_id;
uint32_t mask;
uint8_t data[8];
uint8_t dlc;
uint8_t msgobj;
} CCAN_MSG_OBJ_T;
/**************************************************************************
SDO Abort Codes
**************************************************************************/
#define SDO_ABORT_TOGGLE 0x05030000UL // Toggle bit not alternated
#define SDO_ABORT_SDOTIMEOUT 0x05040000UL // SDO protocol timed out
#define SDO_ABORT_UNKNOWN_COMMAND 0x05040001UL // Client/server command specifier not valid or unknown
#define SDO_ABORT_UNSUPPORTED 0x06010000UL // Unsupported access to an object
#define SDO_ABORT_WRITEONLY 0x06010001UL // Attempt to read a write only object
#define SDO_ABORT_READONLY 0x06010002UL // Attempt to write a read only object
#define SDO_ABORT_NOT_EXISTS 0x06020000UL // Object does not exist in the object dictionary
#define SDO_ABORT_PARAINCOMP 0x06040043UL // General parameter incompatibility reason
#define SDO_ABORT_ACCINCOMP 0x06040047UL // General internal incompatibility in the device
#define SDO_ABORT_TYPEMISMATCH 0x06070010UL // Data type does not match, length of service parameter does not match
#define SDO_ABORT_UNKNOWNSUB 0x06090011UL // Sub-index does not exist
#define SDO_ABORT_VALUE_RANGE 0x06090030UL // Value range of parameter exceeded (only for write access)
#define SDO_ABORT_TRANSFER 0x08000020UL // Data cannot be transferred or stored to the application
#define SDO_ABORT_LOCAL 0x08000021UL // Data cannot be transferred or stored to the application because of local control
#define SDO_ABORT_DEVSTAT 0x08000022UL // Data cannot be transferred or stored to the application because of the present device state
typedef struct CCAN_ODCONSTENTRY {
uint16_t index;
uint8_t subindex;
uint8_t len;
uint32_t val;
} CCAN_ODCONSTENTRY_T;
// upper-nibble values for CAN_ODENTRY.entrytype_len
#define OD_NONE 0x00 // Object Dictionary entry doesn't exist
#define OD_EXP_RO 0x10 // Object Dictionary entry expedited, read-only
#define OD_EXP_WO 0x20 // Object Dictionary entry expedited, write-only
#define OD_EXP_RW 0x30 // Object Dictionary entry expedited, read-write
#define OD_SEG_RO 0x40 // Object Dictionary entry segmented, read-only
#define OD_SEG_WO 0x50 // Object Dictionary entry segmented, write-only
#define OD_SEG_RW 0x60 // Object Dictionary entry segmented, read-write
typedef struct CCAN_ODENTRY {
uint16_t index;
uint8_t subindex;
uint8_t entrytype_len;
uint8_t *val;
} CCAN_ODENTRY_T;
typedef struct CCAN_CANOPENCFG {
uint8_t node_id;
uint8_t msgobj_rx;
uint8_t msgobj_tx;
uint8_t isr_handled;
uint32_t od_const_num;
CCAN_ODCONSTENTRY_T *od_const_table;
uint32_t od_num;
CCAN_ODENTRY_T *od_table;
} CCAN_CANOPENCFG_T;
// Return values for CANOPEN_sdo_req() callback
#define CAN_SDOREQ_NOTHANDLED 0 // process regularly, no impact
#define CAN_SDOREQ_HANDLED_SEND 1 // processed in callback, auto-send returned msg
#define CAN_SDOREQ_HANDLED_NOSEND 2 // processed in callback, don't send response
// Values for CANOPEN_sdo_seg_read/write() callback 'openclose' parameter
#define CAN_SDOSEG_SEGMENT 0 // segment read/write
#define CAN_SDOSEG_OPEN 1 // channel is opened
#define CAN_SDOSEG_CLOSE 2 // channel is closed
typedef struct CCAN_CALLBACKS {
void (*CAN_rx)(uint8_t msg_obj_num);
void (*CAN_tx)(uint8_t msg_obj_num);
void (*CAN_error)(uint32_t error_info);
uint32_t (*CANOPEN_sdo_read)(uint16_t index, uint8_t subindex);
uint32_t (*CANOPEN_sdo_write)(uint16_t index, uint8_t subindex, uint8_t *dat_ptr);
uint32_t (*CANOPEN_sdo_seg_read)(uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t *length,
uint8_t *data, uint8_t *last);
uint32_t (*CANOPEN_sdo_seg_write)(uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t length,
uint8_t *data, uint8_t *fast_resp);
uint8_t (*CANOPEN_sdo_req)(uint8_t length_req, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr);
} CCAN_CALLBACKS_T;
typedef struct CCAN_API {
void (*init_can)(uint32_t *can_cfg, uint8_t isr_ena);
void (*isr)(void);
void (*config_rxmsgobj)(CCAN_MSG_OBJ_T *msg_obj);
uint8_t (*can_receive)(CCAN_MSG_OBJ_T *msg_obj);
void (*can_transmit)(CCAN_MSG_OBJ_T *msg_obj);
void (*config_canopen)(CCAN_CANOPENCFG_T *canopen_cfg);
void (*canopen_handler)(void);
void (*config_calb)(CCAN_CALLBACKS_T *callback_cfg);
} CCAN_API_T;
#define LPC_CCAN_API ((CCAN_API_T *) (LPC_ROM_API->candApiBase))
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CCAND_11XX_H_ */
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/*
* @brief LPC11xx selective CMSIS inclusion file
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_H_
#define __CMSIS_H_
#include "lpc_types.h"
#include "sys_config.h"
/* Select correct CMSIS include file based on CHIP_* definition */
#if defined(CHIP_LPC110X)
#include "cmsis_110x.h"
typedef LPC110X_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC1125)
#include "cmsis_1125.h"
typedef LPC1125_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11AXX)
#include "cmsis_11axx.h"
typedef LPC11AXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11CXX)
#include "cmsis_11cxx.h"
typedef LPC11CXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11EXX)
#include "cmsis_11exx.h"
typedef LPC11EXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11UXX)
#include "cmsis_11uxx.h"
typedef LPC11UXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11XXLV)
#include "cmsis_11lvxx.h"
typedef LPC11XXLV_IRQn_Type IRQn_Type;
#else
#error "No CHIP_* definition is defined"
#endif
/* Cortex-M0 processor and core peripherals */
#include "core_cm0.h"
#endif /* __CMSIS_H_ */
/*
* @brief Basic CMSIS include file for LPC11CXX
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_11CXX_H_
#define __CMSIS_11CXX_H_
#include "lpc_types.h"
#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CMSIS_11CXX CHIP: LPC11Cxx CMSIS include file
* @ingroup CHIP_11XX_CMSIS_Drivers
* Applies to LPC1111, LPC1112, LPC1113, LPC1114, LPC11D14, LPC1115,
* LPC11C12, LPC11C13, LPC11C22, and LPC11C34 devices.
* @{
*/
#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
#pragma diag_suppress 2525
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
// #pragma push // FIXME not usable for IAR
#pragma language=extended
#else
#error Not supported compiler type
#endif
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
#if !defined(CHIP_LPC11CXX)
#error Incorrect or missing device variant (CHIP_LPC11AXX)
#endif
/** @defgroup CMSIS_11CXX_IRQ CHIP_LPC11CXX: LPC11CXX/LPC111X peripheral interrupt numbers
* @{
*/
typedef enum LPC11CXX_IRQn {
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
PIO0_0_IRQn = 0, /*!< GPIO port 0, pin 0 Interrupt */
PIO0_1_IRQn = 1, /*!< GPIO port 0, pin 1 Interrupt */
PIO0_2_IRQn = 2, /*!< GPIO port 0, pin 2 Interrupt */
PIO0_3_IRQn = 3, /*!< GPIO port 0, pin 3 Interrupt */
PIO0_4_IRQn = 4, /*!< GPIO port 0, pin 4 Interrupt */
PIO0_5_IRQn = 5, /*!< GPIO port 0, pin 5 Interrupt */
PIO0_6_IRQn = 6, /*!< GPIO port 0, pin 6 Interrupt */
PIO0_7_IRQn = 7, /*!< GPIO port 0, pin 7 Interrupt */
PIO0_8_IRQn = 8, /*!< GPIO port 0, pin 8 Interrupt */
PIO0_9_IRQn = 9, /*!< GPIO port 0, pin 9 Interrupt */
PIO0_10_IRQn = 10, /*!< GPIO port 0, pin 10 Interrupt */
PIO0_11_IRQn = 11, /*!< GPIO port 0, pin 11 Interrupt */
PIO1_0_IRQn = 12, /*!< GPIO port 1, pin 0 Interrupt */
CAN_IRQn = 13, /*!< CAN Interrupt */
SSP1_IRQn = 14, /*!< SSP1 Interrupt */
I2C0_IRQn = 15, /*!< I2C Interrupt */
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /*!< SSP0 Interrupt */
UART0_IRQn = 21, /*!< UART Interrupt */
Reserved22_IRQn = 22,
Reserved23_IRQn = 23,
ADC_IRQn = 24, /*!< A/D Converter Interrupt */
WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
Reserved27_IRQn = 27,
EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
} LPC11CXX_IRQn_Type;
/**
* @}
*/
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/** @defgroup CMSIS_11CXX_COMMON CHIP: LPC11Cxx Cortex CMSIS definitions
* @{
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_11CXX_H_ */
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/*
* @brief Error code returned by Boot ROM drivers/library functions
* @ingroup Common
*
* This file contains unified error codes to be used across driver,
* middleware, applications, hal and demo software.
*
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_ERROR_H__
#define __LPC_ERROR_H__
/** Error code returned by Boot ROM drivers/library functions
*
* Error codes are a 32-bit value with :
* - The 16 MSB contains the peripheral code number
* - The 16 LSB contains an error code number associated to that peripheral
*
*/
typedef enum
{
/**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */
/**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */
/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */
/**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */
/* ISP related errors */
ERR_ISP_BASE = 0x00000000,
/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
/*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
/*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */
/*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
/*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
/*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
/*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */
/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
/* ROM API related errors */
ERR_API_BASE = 0x00010000,
/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/
/**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */
/**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */
/**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */
/**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */
/* SPIFI API related errors */
ERR_SPIFI_BASE = 0x00020000,
/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1,
/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
/*0x00020003*/ ERR_SPIFI_TIMEOUT,
/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
/* Security API related errors */
ERR_SEC_BASE = 0x00030000,
/*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_BASE+1,
/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
/* USB device stack related errors */
ERR_USBD_BASE = 0x00040000,
/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */
/**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */
/**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */
/**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */
/**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */
/**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/
/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/
/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/
/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */
/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */
/* CGU related errors */
ERR_CGU_BASE = 0x00050000,
/*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1,
/*0x00050002*/ ERR_CGU_INVALID_PARAM,
/*0x00050003*/ ERR_CGU_INVALID_SLICE,
/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
/*0x00050005*/ ERR_CGU_DIV_SRC,
/*0x00050006*/ ERR_CGU_DIV_VAL,
/*0x00050007*/ ERR_CGU_SRC
} ErrorCode_t;
//#define offsetof(s,m) (int)&(((s *)0)->m)
#define COMPILE_TIME_ASSERT(pred) switch(0){case 0:case pred:;}
#endif /* __LPC_ERROR_H__ */
/*
* @brief FLASH Memory Controller (FMC) registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __FMC_11XX_H_
#define __FMC_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup FMC_11XX CHIP: LPC11xx FLASH Memory Controller driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief FLASH Memory Controller Unit register block structure
*/
typedef struct {/*!< FMC Structure */
__I uint32_t RESERVED1[4];
__IO uint32_t FLASHTIM;
__I uint32_t RESERVED2[3];
__IO uint32_t FMSSTART;
__IO uint32_t FMSSTOP;
__I uint32_t RESERVED3;
__I uint32_t FMSW[4];
__I uint32_t RESERVED4[25];
#if defined(CHIP_LPC1125)
__I uint32_t RESERVED5[977];
#else
__IO uint32_t EEMSSTART;
__IO uint32_t EEMSSTOP;
__I uint32_t EEMSSIG;
__I uint32_t RESERVED5[974];
#endif
__I uint32_t FMSTAT;
__I uint32_t RESERVED6;
__O uint32_t FMSTATCLR;
} LPC_FMC_T;
/**
* @brief FLASH Access time definitions
*/
typedef enum {
FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/
FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock*/
FLASHTIM_50MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 50 MHz CPU clock*/
} FMC_FLASHTIM_T;
/**
* @brief Set FLASH access time in clocks
* @param clks : Clock cycles for FLASH access (minus 1)
* @return Nothing
* @note For CPU speed up to 20MHz, use a value of 0. For up to 40MHz, use
* a value of 1. For up to 50MHz, use a value of 2.
*/
STATIC INLINE void Chip_FMC_SetFLASHAccess(FMC_FLASHTIM_T clks)
{
uint32_t tmp = LPC_FMC->FLASHTIM & (~(0x3));
/* Don't alter upper bits */
LPC_FMC->FLASHTIM = tmp | clks;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FMC_11XX_H_ */
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/*
* @brief LPC11xx GPIO group driver for CHIP_LPC11AXX, CHIP_LPC11EXX, and
* CHIP_LPC11UXX families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIOGROUP_11XX_H_
#define __GPIOGROUP_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIOGP_11XX CHIP: LPC11xx GPIO group driver for CHIP_LPC11(A/E/U)XX families
* @ingroup CHIP_11XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC11AXX,
* CHIP_LPC11EXX, and CHIP_LPC11UXX only.
* @{
*/
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief GPIO grouped interrupt register block structure
*/
typedef struct { /*!< GPIO_GROUP_INTn Structure */
__IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
__IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
uint32_t RESERVED1[4072];
} LPC_GPIOGROUPINT_T;
/**
* LPC11xx GPIO group bit definitions
*/
#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */
#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */
#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */
/**
* @brief Clear interrupt pending status for the selected group
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
uint32_t temp;
temp = pGPIOGPINT[group].CTRL;
pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
}
/**
* @brief Returns current GPIO group inetrrupt pending status
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return true if the group interrupt is pending, otherwise false.
*/
STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
}